/**
 * @file
 * @brief  The generated interface for the register allocator.
 *          Contains register classes and types and register constraints
 *          for all nodes where constraints were given in spec.
 * @note    DO NOT EDIT THIS FILE, your changes will be lost.
 *          Edit ./ir/be/ia32/ia32_spec.pl instead.
 *          created by: ./ir/be/scripts/generate_regalloc_if.pl ./ir/be/ia32/ia32_spec.pl build/gen/ir/be/ia32
 * $date    Tue Jul  7 23:51:18 2026
 */
#include "gen_ia32_regalloc_if.h"

#include "ia32_bearch_t.h"

const arch_register_req_t ia32_class_reg_req_flags = {
	.cls   = &ia32_reg_classes[CLASS_ia32_flags],
	.width = 1,
};
static const unsigned ia32_limited_flags_eflags[] = { (1U << REG_FLAGS_EFLAGS) };
const arch_register_req_t ia32_single_reg_req_flags_eflags = {
	.cls     = &ia32_reg_classes[CLASS_ia32_flags],
	.limited = ia32_limited_flags_eflags,
	.width   = 1,
};
const arch_register_req_t ia32_class_reg_req_fp = {
	.cls   = &ia32_reg_classes[CLASS_ia32_fp],
	.width = 1,
};
static const unsigned ia32_limited_fp_st0[] = { (1U << REG_FP_ST0) };
const arch_register_req_t ia32_single_reg_req_fp_st0 = {
	.cls     = &ia32_reg_classes[CLASS_ia32_fp],
	.limited = ia32_limited_fp_st0,
	.width   = 1,
};
static const unsigned ia32_limited_fp_st1[] = { (1U << REG_FP_ST1) };
const arch_register_req_t ia32_single_reg_req_fp_st1 = {
	.cls     = &ia32_reg_classes[CLASS_ia32_fp],
	.limited = ia32_limited_fp_st1,
	.width   = 1,
};
static const unsigned ia32_limited_fp_st2[] = { (1U << REG_FP_ST2) };
const arch_register_req_t ia32_single_reg_req_fp_st2 = {
	.cls     = &ia32_reg_classes[CLASS_ia32_fp],
	.limited = ia32_limited_fp_st2,
	.width   = 1,
};
static const unsigned ia32_limited_fp_st3[] = { (1U << REG_FP_ST3) };
const arch_register_req_t ia32_single_reg_req_fp_st3 = {
	.cls     = &ia32_reg_classes[CLASS_ia32_fp],
	.limited = ia32_limited_fp_st3,
	.width   = 1,
};
static const unsigned ia32_limited_fp_st4[] = { (1U << REG_FP_ST4) };
const arch_register_req_t ia32_single_reg_req_fp_st4 = {
	.cls     = &ia32_reg_classes[CLASS_ia32_fp],
	.limited = ia32_limited_fp_st4,
	.width   = 1,
};
static const unsigned ia32_limited_fp_st5[] = { (1U << REG_FP_ST5) };
const arch_register_req_t ia32_single_reg_req_fp_st5 = {
	.cls     = &ia32_reg_classes[CLASS_ia32_fp],
	.limited = ia32_limited_fp_st5,
	.width   = 1,
};
static const unsigned ia32_limited_fp_st6[] = { (1U << REG_FP_ST6) };
const arch_register_req_t ia32_single_reg_req_fp_st6 = {
	.cls     = &ia32_reg_classes[CLASS_ia32_fp],
	.limited = ia32_limited_fp_st6,
	.width   = 1,
};
static const unsigned ia32_limited_fp_st7[] = { (1U << REG_FP_ST7) };
const arch_register_req_t ia32_single_reg_req_fp_st7 = {
	.cls     = &ia32_reg_classes[CLASS_ia32_fp],
	.limited = ia32_limited_fp_st7,
	.width   = 1,
};
static const unsigned ia32_limited_fp_fp_NOREG[] = { (1U << REG_FP_FP_NOREG) };
const arch_register_req_t ia32_single_reg_req_fp_fp_NOREG = {
	.cls     = &ia32_reg_classes[CLASS_ia32_fp],
	.limited = ia32_limited_fp_fp_NOREG,
	.width   = 1,
};
const arch_register_req_t ia32_class_reg_req_fpcw = {
	.cls   = &ia32_reg_classes[CLASS_ia32_fpcw],
	.width = 1,
};
static const unsigned ia32_limited_fpcw_fpcw[] = { (1U << REG_FPCW_FPCW) };
const arch_register_req_t ia32_single_reg_req_fpcw_fpcw = {
	.cls     = &ia32_reg_classes[CLASS_ia32_fpcw],
	.limited = ia32_limited_fpcw_fpcw,
	.width   = 1,
};
const arch_register_req_t ia32_class_reg_req_gp = {
	.cls   = &ia32_reg_classes[CLASS_ia32_gp],
	.width = 1,
};
static const unsigned ia32_limited_gp_edx[] = { (1U << REG_GP_EDX) };
const arch_register_req_t ia32_single_reg_req_gp_edx = {
	.cls     = &ia32_reg_classes[CLASS_ia32_gp],
	.limited = ia32_limited_gp_edx,
	.width   = 1,
};
static const unsigned ia32_limited_gp_ecx[] = { (1U << REG_GP_ECX) };
const arch_register_req_t ia32_single_reg_req_gp_ecx = {
	.cls     = &ia32_reg_classes[CLASS_ia32_gp],
	.limited = ia32_limited_gp_ecx,
	.width   = 1,
};
static const unsigned ia32_limited_gp_eax[] = { (1U << REG_GP_EAX) };
const arch_register_req_t ia32_single_reg_req_gp_eax = {
	.cls     = &ia32_reg_classes[CLASS_ia32_gp],
	.limited = ia32_limited_gp_eax,
	.width   = 1,
};
static const unsigned ia32_limited_gp_ebx[] = { (1U << REG_GP_EBX) };
const arch_register_req_t ia32_single_reg_req_gp_ebx = {
	.cls     = &ia32_reg_classes[CLASS_ia32_gp],
	.limited = ia32_limited_gp_ebx,
	.width   = 1,
};
static const unsigned ia32_limited_gp_esi[] = { (1U << REG_GP_ESI) };
const arch_register_req_t ia32_single_reg_req_gp_esi = {
	.cls     = &ia32_reg_classes[CLASS_ia32_gp],
	.limited = ia32_limited_gp_esi,
	.width   = 1,
};
static const unsigned ia32_limited_gp_edi[] = { (1U << REG_GP_EDI) };
const arch_register_req_t ia32_single_reg_req_gp_edi = {
	.cls     = &ia32_reg_classes[CLASS_ia32_gp],
	.limited = ia32_limited_gp_edi,
	.width   = 1,
};
static const unsigned ia32_limited_gp_ebp[] = { (1U << REG_GP_EBP) };
const arch_register_req_t ia32_single_reg_req_gp_ebp = {
	.cls     = &ia32_reg_classes[CLASS_ia32_gp],
	.limited = ia32_limited_gp_ebp,
	.width   = 1,
};
static const unsigned ia32_limited_gp_esp[] = { (1U << REG_GP_ESP) };
const arch_register_req_t ia32_single_reg_req_gp_esp = {
	.cls     = &ia32_reg_classes[CLASS_ia32_gp],
	.limited = ia32_limited_gp_esp,
	.width   = 1,
};
static const unsigned ia32_limited_gp_gp_NOREG[] = { (1U << REG_GP_GP_NOREG) };
const arch_register_req_t ia32_single_reg_req_gp_gp_NOREG = {
	.cls     = &ia32_reg_classes[CLASS_ia32_gp],
	.limited = ia32_limited_gp_gp_NOREG,
	.width   = 1,
};
const arch_register_req_t ia32_class_reg_req_xmm = {
	.cls   = &ia32_reg_classes[CLASS_ia32_xmm],
	.width = 1,
};
static const unsigned ia32_limited_xmm_xmm0[] = { (1U << REG_XMM_XMM0) };
const arch_register_req_t ia32_single_reg_req_xmm_xmm0 = {
	.cls     = &ia32_reg_classes[CLASS_ia32_xmm],
	.limited = ia32_limited_xmm_xmm0,
	.width   = 1,
};
static const unsigned ia32_limited_xmm_xmm1[] = { (1U << REG_XMM_XMM1) };
const arch_register_req_t ia32_single_reg_req_xmm_xmm1 = {
	.cls     = &ia32_reg_classes[CLASS_ia32_xmm],
	.limited = ia32_limited_xmm_xmm1,
	.width   = 1,
};
static const unsigned ia32_limited_xmm_xmm2[] = { (1U << REG_XMM_XMM2) };
const arch_register_req_t ia32_single_reg_req_xmm_xmm2 = {
	.cls     = &ia32_reg_classes[CLASS_ia32_xmm],
	.limited = ia32_limited_xmm_xmm2,
	.width   = 1,
};
static const unsigned ia32_limited_xmm_xmm3[] = { (1U << REG_XMM_XMM3) };
const arch_register_req_t ia32_single_reg_req_xmm_xmm3 = {
	.cls     = &ia32_reg_classes[CLASS_ia32_xmm],
	.limited = ia32_limited_xmm_xmm3,
	.width   = 1,
};
static const unsigned ia32_limited_xmm_xmm4[] = { (1U << REG_XMM_XMM4) };
const arch_register_req_t ia32_single_reg_req_xmm_xmm4 = {
	.cls     = &ia32_reg_classes[CLASS_ia32_xmm],
	.limited = ia32_limited_xmm_xmm4,
	.width   = 1,
};
static const unsigned ia32_limited_xmm_xmm5[] = { (1U << REG_XMM_XMM5) };
const arch_register_req_t ia32_single_reg_req_xmm_xmm5 = {
	.cls     = &ia32_reg_classes[CLASS_ia32_xmm],
	.limited = ia32_limited_xmm_xmm5,
	.width   = 1,
};
static const unsigned ia32_limited_xmm_xmm6[] = { (1U << REG_XMM_XMM6) };
const arch_register_req_t ia32_single_reg_req_xmm_xmm6 = {
	.cls     = &ia32_reg_classes[CLASS_ia32_xmm],
	.limited = ia32_limited_xmm_xmm6,
	.width   = 1,
};
static const unsigned ia32_limited_xmm_xmm7[] = { (1U << REG_XMM_XMM7) };
const arch_register_req_t ia32_single_reg_req_xmm_xmm7 = {
	.cls     = &ia32_reg_classes[CLASS_ia32_xmm],
	.limited = ia32_limited_xmm_xmm7,
	.width   = 1,
};
static const unsigned ia32_limited_xmm_xmm_NOREG[] = { (1U << REG_XMM_XMM_NOREG) };
const arch_register_req_t ia32_single_reg_req_xmm_xmm_NOREG = {
	.cls     = &ia32_reg_classes[CLASS_ia32_xmm],
	.limited = ia32_limited_xmm_xmm_NOREG,
	.width   = 1,
};


arch_register_class_t ia32_reg_classes[] = {
	{
		.name      = "ia32_flags",
		.mode      = NULL,
		.regs      = &ia32_registers[REG_EFLAGS],
		.class_req = &ia32_class_reg_req_flags,
		.index     = CLASS_ia32_flags,
		.n_regs    = 1,
		.manual_ra = true,
	},
	{
		.name      = "ia32_fp",
		.mode      = NULL,
		.regs      = &ia32_registers[REG_ST0],
		.class_req = &ia32_class_reg_req_fp,
		.index     = CLASS_ia32_fp,
		.n_regs    = 9,
		.allow_clobber_input = true,
	},
	{
		.name      = "ia32_fpcw",
		.mode      = NULL,
		.regs      = &ia32_registers[REG_FPCW],
		.class_req = &ia32_class_reg_req_fpcw,
		.index     = CLASS_ia32_fpcw,
		.n_regs    = 1,
		.manual_ra = true,
	},
	{
		.name      = "ia32_gp",
		.mode      = NULL,
		.regs      = &ia32_registers[REG_EDX],
		.class_req = &ia32_class_reg_req_gp,
		.index     = CLASS_ia32_gp,
		.n_regs    = 9,
	},
	{
		.name      = "ia32_xmm",
		.mode      = NULL,
		.regs      = &ia32_registers[REG_XMM0],
		.class_req = &ia32_class_reg_req_xmm,
		.index     = CLASS_ia32_xmm,
		.n_regs    = 9,
	},

};

/** The array of all registers in the ia32 architecture, sorted by its global index.*/
const arch_register_t ia32_registers[] = {
	{
		.name         = "eflags",
		.cls          = &ia32_reg_classes[CLASS_ia32_flags],
		.single_req   = &ia32_single_reg_req_flags_eflags,
		.index        = REG_FLAGS_EFLAGS,
		.global_index = REG_EFLAGS,
		.dwarf_number = 9,
		.encoding     = REG_FLAGS_EFLAGS,
		.is_virtual   = false,
	},
	{
		.name         = "st",
		.cls          = &ia32_reg_classes[CLASS_ia32_fp],
		.single_req   = &ia32_single_reg_req_fp_st0,
		.index        = REG_FP_ST0,
		.global_index = REG_ST0,
		.dwarf_number = 11,
		.encoding     = 0,
		.is_virtual   = false,
	},
	{
		.name         = "st(1)",
		.cls          = &ia32_reg_classes[CLASS_ia32_fp],
		.single_req   = &ia32_single_reg_req_fp_st1,
		.index        = REG_FP_ST1,
		.global_index = REG_ST1,
		.dwarf_number = 12,
		.encoding     = 1,
		.is_virtual   = false,
	},
	{
		.name         = "st(2)",
		.cls          = &ia32_reg_classes[CLASS_ia32_fp],
		.single_req   = &ia32_single_reg_req_fp_st2,
		.index        = REG_FP_ST2,
		.global_index = REG_ST2,
		.dwarf_number = 13,
		.encoding     = 2,
		.is_virtual   = false,
	},
	{
		.name         = "st(3)",
		.cls          = &ia32_reg_classes[CLASS_ia32_fp],
		.single_req   = &ia32_single_reg_req_fp_st3,
		.index        = REG_FP_ST3,
		.global_index = REG_ST3,
		.dwarf_number = 14,
		.encoding     = 3,
		.is_virtual   = false,
	},
	{
		.name         = "st(4)",
		.cls          = &ia32_reg_classes[CLASS_ia32_fp],
		.single_req   = &ia32_single_reg_req_fp_st4,
		.index        = REG_FP_ST4,
		.global_index = REG_ST4,
		.dwarf_number = 15,
		.encoding     = 4,
		.is_virtual   = false,
	},
	{
		.name         = "st(5)",
		.cls          = &ia32_reg_classes[CLASS_ia32_fp],
		.single_req   = &ia32_single_reg_req_fp_st5,
		.index        = REG_FP_ST5,
		.global_index = REG_ST5,
		.dwarf_number = 16,
		.encoding     = 5,
		.is_virtual   = false,
	},
	{
		.name         = "st(6)",
		.cls          = &ia32_reg_classes[CLASS_ia32_fp],
		.single_req   = &ia32_single_reg_req_fp_st6,
		.index        = REG_FP_ST6,
		.global_index = REG_ST6,
		.dwarf_number = 17,
		.encoding     = 6,
		.is_virtual   = false,
	},
	{
		.name         = "st(7)",
		.cls          = &ia32_reg_classes[CLASS_ia32_fp],
		.single_req   = &ia32_single_reg_req_fp_st7,
		.index        = REG_FP_ST7,
		.global_index = REG_ST7,
		.dwarf_number = 18,
		.encoding     = 7,
		.is_virtual   = false,
	},
	{
		.name         = "fp_NOREG",
		.cls          = &ia32_reg_classes[CLASS_ia32_fp],
		.single_req   = &ia32_single_reg_req_fp_fp_NOREG,
		.index        = REG_FP_FP_NOREG,
		.global_index = REG_FP_NOREG,
		.dwarf_number = 0,
		.encoding     = REG_FP_FP_NOREG,
		.is_virtual   = true,
	},
	{
		.name         = "fpcw",
		.cls          = &ia32_reg_classes[CLASS_ia32_fpcw],
		.single_req   = &ia32_single_reg_req_fpcw_fpcw,
		.index        = REG_FPCW_FPCW,
		.global_index = REG_FPCW,
		.dwarf_number = 37,
		.encoding     = REG_FPCW_FPCW,
		.is_virtual   = false,
	},
	{
		.name         = "edx",
		.cls          = &ia32_reg_classes[CLASS_ia32_gp],
		.single_req   = &ia32_single_reg_req_gp_edx,
		.index        = REG_GP_EDX,
		.global_index = REG_EDX,
		.dwarf_number = 2,
		.encoding     = 2,
		.is_virtual   = false,
	},
	{
		.name         = "ecx",
		.cls          = &ia32_reg_classes[CLASS_ia32_gp],
		.single_req   = &ia32_single_reg_req_gp_ecx,
		.index        = REG_GP_ECX,
		.global_index = REG_ECX,
		.dwarf_number = 1,
		.encoding     = 1,
		.is_virtual   = false,
	},
	{
		.name         = "eax",
		.cls          = &ia32_reg_classes[CLASS_ia32_gp],
		.single_req   = &ia32_single_reg_req_gp_eax,
		.index        = REG_GP_EAX,
		.global_index = REG_EAX,
		.dwarf_number = 0,
		.encoding     = 0,
		.is_virtual   = false,
	},
	{
		.name         = "ebx",
		.cls          = &ia32_reg_classes[CLASS_ia32_gp],
		.single_req   = &ia32_single_reg_req_gp_ebx,
		.index        = REG_GP_EBX,
		.global_index = REG_EBX,
		.dwarf_number = 3,
		.encoding     = 3,
		.is_virtual   = false,
	},
	{
		.name         = "esi",
		.cls          = &ia32_reg_classes[CLASS_ia32_gp],
		.single_req   = &ia32_single_reg_req_gp_esi,
		.index        = REG_GP_ESI,
		.global_index = REG_ESI,
		.dwarf_number = 6,
		.encoding     = 6,
		.is_virtual   = false,
	},
	{
		.name         = "edi",
		.cls          = &ia32_reg_classes[CLASS_ia32_gp],
		.single_req   = &ia32_single_reg_req_gp_edi,
		.index        = REG_GP_EDI,
		.global_index = REG_EDI,
		.dwarf_number = 7,
		.encoding     = 7,
		.is_virtual   = false,
	},
	{
		.name         = "ebp",
		.cls          = &ia32_reg_classes[CLASS_ia32_gp],
		.single_req   = &ia32_single_reg_req_gp_ebp,
		.index        = REG_GP_EBP,
		.global_index = REG_EBP,
		.dwarf_number = 5,
		.encoding     = 5,
		.is_virtual   = false,
	},
	{
		.name         = "esp",
		.cls          = &ia32_reg_classes[CLASS_ia32_gp],
		.single_req   = &ia32_single_reg_req_gp_esp,
		.index        = REG_GP_ESP,
		.global_index = REG_ESP,
		.dwarf_number = 4,
		.encoding     = 4,
		.is_virtual   = false,
	},
	{
		.name         = "gp_NOREG",
		.cls          = &ia32_reg_classes[CLASS_ia32_gp],
		.single_req   = &ia32_single_reg_req_gp_gp_NOREG,
		.index        = REG_GP_GP_NOREG,
		.global_index = REG_GP_NOREG,
		.dwarf_number = 0,
		.encoding     = REG_GP_GP_NOREG,
		.is_virtual   = true,
	},
	{
		.name         = "xmm0",
		.cls          = &ia32_reg_classes[CLASS_ia32_xmm],
		.single_req   = &ia32_single_reg_req_xmm_xmm0,
		.index        = REG_XMM_XMM0,
		.global_index = REG_XMM0,
		.dwarf_number = 21,
		.encoding     = REG_XMM_XMM0,
		.is_virtual   = false,
	},
	{
		.name         = "xmm1",
		.cls          = &ia32_reg_classes[CLASS_ia32_xmm],
		.single_req   = &ia32_single_reg_req_xmm_xmm1,
		.index        = REG_XMM_XMM1,
		.global_index = REG_XMM1,
		.dwarf_number = 22,
		.encoding     = REG_XMM_XMM1,
		.is_virtual   = false,
	},
	{
		.name         = "xmm2",
		.cls          = &ia32_reg_classes[CLASS_ia32_xmm],
		.single_req   = &ia32_single_reg_req_xmm_xmm2,
		.index        = REG_XMM_XMM2,
		.global_index = REG_XMM2,
		.dwarf_number = 23,
		.encoding     = REG_XMM_XMM2,
		.is_virtual   = false,
	},
	{
		.name         = "xmm3",
		.cls          = &ia32_reg_classes[CLASS_ia32_xmm],
		.single_req   = &ia32_single_reg_req_xmm_xmm3,
		.index        = REG_XMM_XMM3,
		.global_index = REG_XMM3,
		.dwarf_number = 24,
		.encoding     = REG_XMM_XMM3,
		.is_virtual   = false,
	},
	{
		.name         = "xmm4",
		.cls          = &ia32_reg_classes[CLASS_ia32_xmm],
		.single_req   = &ia32_single_reg_req_xmm_xmm4,
		.index        = REG_XMM_XMM4,
		.global_index = REG_XMM4,
		.dwarf_number = 25,
		.encoding     = REG_XMM_XMM4,
		.is_virtual   = false,
	},
	{
		.name         = "xmm5",
		.cls          = &ia32_reg_classes[CLASS_ia32_xmm],
		.single_req   = &ia32_single_reg_req_xmm_xmm5,
		.index        = REG_XMM_XMM5,
		.global_index = REG_XMM5,
		.dwarf_number = 26,
		.encoding     = REG_XMM_XMM5,
		.is_virtual   = false,
	},
	{
		.name         = "xmm6",
		.cls          = &ia32_reg_classes[CLASS_ia32_xmm],
		.single_req   = &ia32_single_reg_req_xmm_xmm6,
		.index        = REG_XMM_XMM6,
		.global_index = REG_XMM6,
		.dwarf_number = 27,
		.encoding     = REG_XMM_XMM6,
		.is_virtual   = false,
	},
	{
		.name         = "xmm7",
		.cls          = &ia32_reg_classes[CLASS_ia32_xmm],
		.single_req   = &ia32_single_reg_req_xmm_xmm7,
		.index        = REG_XMM_XMM7,
		.global_index = REG_XMM7,
		.dwarf_number = 28,
		.encoding     = REG_XMM_XMM7,
		.is_virtual   = false,
	},
	{
		.name         = "xmm_NOREG",
		.cls          = &ia32_reg_classes[CLASS_ia32_xmm],
		.single_req   = &ia32_single_reg_req_xmm_xmm_NOREG,
		.index        = REG_XMM_XMM_NOREG,
		.global_index = REG_XMM_NOREG,
		.dwarf_number = 0,
		.encoding     = REG_XMM_XMM_NOREG,
		.is_virtual   = true,
	},

};

/**
 * Initializes ia32 register classes.
 */
void ia32_register_init(void)
{
	ia32_reg_classes[CLASS_ia32_flags].mode = ia32_mode_flags;
	ia32_reg_classes[CLASS_ia32_fp].mode = x86_mode_E;
	ia32_reg_classes[CLASS_ia32_fpcw].mode = ia32_mode_fpcw;
	ia32_reg_classes[CLASS_ia32_gp].mode = ia32_mode_gp;
	ia32_reg_classes[CLASS_ia32_xmm].mode = ia32_mode_float64;

}
