PIC18LF1330
Author: Molnár Károly

All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size ROM
size EEPROM
size Common
SFRs
Features Configuration Bits RAM map SFR map

PIC18LF1330
CONFIG1H (address:0x300001, mask:0xCF, default:0x07)
OSC -- Oscillator (bitmask:0x0F)
OSC = LP | 0xF0 | LP Oscillator.
OSC = XT | 0xF1 | XT Oscillator.
OSC = HS | 0xF2 | HS Oscillator.
OSC = RC | 0xF3 | External RC oscillator, CLKO function on RA6.
OSC = EC | 0xF4 | EC oscillator, CLKO function on RA6.
OSC = ECIO | 0xF5 | EC oscillator, port function on RA6.
OSC = HSPLL | 0xF6 | HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1).
OSC = RCIO | 0xF7 | External RC oscillator, port function on RA6.
OSC = INTIO2 | 0xF8 | Internal oscillator, port function on RA6 and RA7.
OSC = INTIO1 | 0xF9 | Internal oscillator, CLKO function on RA6, port function on RA7.
FCMEN -- Fail-Safe Clock Monitor Enable bit (bitmask:0x40)
FCMEN = OFF | 0xBF | Fail-Safe Clock Monitor disabled.
FCMEN = ON | 0xFF | Fail-Safe Clock Monitor enabled.
IESO -- Internal/External Oscillator Switchover bit (bitmask:0x80)
IESO = OFF | 0x7F | Oscillator Switchover mode disabled.
IESO = ON | 0xFF | Oscillator Switchover mode enabled.
CONFIG2L (address:0x300002, mask:0x1F, default:0x1F)
PWRT -- Power-up Timer Enable bit (bitmask:0x01)
PWRT = ON | 0xFE | PWRT enabled.
PWRT = OFF | 0xFF | PWRT disabled.
BOR -- Brown-out Reset Enable bits (bitmask:0x06)
BOR = OFF | 0xF9 | Brown-out Reset disabled in hardware and software.
BOR = SBORENCTRL | 0xFB | Brown-out Reset enabled and controlled by software (SBOREN is enabled).
BOR = BOACTIVE | 0xFD | Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled).
BOR = BOHW | 0xFF | Brown-out Reset enabled in hardware only (SBOREN is disabled).
BORV -- Brown-out Reset Voltage bits (bitmask:0x18)
BORV = 0 | 0xE7 | Maximum setting.
BORV = 1 | 0xEF |
BORV = 2 | 0xF7 |
BORV = 3 | 0xFF | Minimum setting.
CONFIG2H (address:0x300003, mask:0x1F, default:0x1F)
WDT -- Watchdog Timer Enable bit (bitmask:0x01)
WDT = OFF | 0xFE | WDT disabled (control is placed on the SWDTEN bit).
WDT = ON | 0xFF | WDT enabled.
WDTPS -- Watchdog Timer Postscale Select bits (bitmask:0x1E)
WDTPS = 1 | 0xE1 | 1:1.
WDTPS = 2 | 0xE3 | 1:2.
WDTPS = 4 | 0xE5 | 1:4.
WDTPS = 8 | 0xE7 | 1:8.
WDTPS = 16 | 0xE9 | 1:16.
WDTPS = 32 | 0xEB | 1:32.
WDTPS = 64 | 0xED | 1:64.
WDTPS = 128 | 0xEF | 1:128.
WDTPS = 256 | 0xF1 | 1:256.
WDTPS = 512 | 0xF3 | 1:512.
WDTPS = 1024 | 0xF5 | 1:1024.
WDTPS = 2048 | 0xF7 | 1:2048.
WDTPS = 4096 | 0xF9 | 1:4096.
WDTPS = 8192 | 0xFB | 1:8192.
WDTPS = 16384 | 0xFD | 1:16384.
WDTPS = 32768 | 0xFF | 1:32768.
CONFIG3L (address:0x300004, mask:0x0E, default:0x0E)
PWMPIN -- PWM Output Pins Reset State Control bit (bitmask:0x02)
PWMPIN = ON | 0xFD | PWM outputs drive active states upon Reset.
PWMPIN = OFF | 0xFF | PWM outputs disabled upon Reset.
LPOL -- Low-Side Transistors Polarity bit (Even PWM Output Polarity Control bit) (bitmask:0x04)
LPOL = LOW | 0xFB | PWM0, PWM2 and PWM4 are active-low.
LPOL = HIGH | 0xFF | PWM0, PWM2 and PWM4 are active-high (default).
HPOL -- High Side Transistors Polarity bit (Odd PWM Output Polarity Control bit) (bitmask:0x08)
HPOL = LOW | 0xF7 | PWM1, PWM3 and PWM5 are active-low.
HPOL = HIGH | 0xFF | PWM1, PWM3 and PWM5 are active-high (default).
CONFIG3H (address:0x300005, mask:0x89, default:0x81)
FLTAMX -- FLTA Mux bit (bitmask:0x01)
FLTAMX = RA7 | 0xFE | FLTA input is muxed onto RA7.
FLTAMX = RA5 | 0xFF | FLTA input is muxed onto RA5.
T1OSCMX -- T1OSO/T1CKI MUX bit (bitmask:0x08)
T1OSCMX = LOW | 0xF7 | T1OSO/T1CKI pin resides on RB2.
T1OSCMX = HIGH | 0xFF | T1OSO/T1CKI pin resides on RA6.
MCLRE -- Master Clear Enable bit (bitmask:0x80)
MCLRE = OFF | 0x7F | RA5 input pin enabled, MCLR pin disabled.
MCLRE = ON | 0xFF | MCLR pin enabled, RA5 input pin disabled.
CONFIG4L (address:0x300006, mask:0xF1, default:0x81)
STVREN -- Stack Overflow/Underflow Reset Enable bit (bitmask:0x01)
STVREN = OFF | 0xFE | Reset on stack overflow/underflow disabled.
STVREN = ON | 0xFF | Reset on stack overflow/underflow enabled.
BBSIZ -- Boot Block Size Select bits (bitmask:0x30)
BBSIZ = BB256 | 0xCF | 256 Words (512 Bytes) Boot Block size.
BBSIZ = BB512 | 0xDF | 512 Words (1024 Bytes) Boot Block size.
BBSIZ = BB1K | 0xFF | 1K Words (2048 Bytes) Boot Block size.
XINST -- Extended Instruction Set Enable bit (bitmask:0x40)
XINST = OFF | 0xBF | Instruction set extension and Indexed Addressing mode disabled.
XINST = ON | 0xFF | Instruction set extension and Indexed Addressing mode enabled.
DEBUG -- Background Debugger Enable bit (bitmask:0x80)
DEBUG = ON | 0x7F | Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug.
DEBUG = OFF | 0xFF | Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins.
CONFIG5L (address:0x300008, mask:0x03, default:0x03)
CP0 -- Code Protection bit Block 0 (000800-000FFF) (bitmask:0x01)
CP0 = ON | 0xFE | Block 0 is code-protected.
CP0 = OFF | 0xFF | Block 0 is not code-protected.
CP1 -- Code Protection bit Block 1 (001000-001FFF) (bitmask:0x02)
CP1 = ON | 0xFD | Block 1 is code-protected.
CP1 = OFF | 0xFF | Block 1 is not code-protected.
CONFIG5H (address:0x300009, mask:0xC0, default:0xC0)
CPB -- Code Protection bit (Boot Block Memory Area) (bitmask:0x40)
CPB = ON | 0xBF | Boot Block is code-protected.
CPB = OFF | 0xFF | Boot Block is not code-protected.
CPD -- Code Protection bit (Data EEPROM) (bitmask:0x80)
CPD = ON | 0x7F | Data EEPROM is code-protected.
CPD = OFF | 0xFF | Data EEPROM is not code-protected.
CONFIG6L (address:0x30000A, mask:0x03, default:0x03)
WRT0 -- Write Protection bit Block 0 (000800-000FFF) (bitmask:0x01)
WRT0 = ON | 0xFE | Block 0 is write-protected.
WRT0 = OFF | 0xFF | Block 0 is not write-protected.
WRT1 -- Write Protection bit Block 1 (001000-001FFF) (bitmask:0x02)
WRT1 = ON | 0xFD | Block 1 is write-protected.
WRT1 = OFF | 0xFF | Block 1 is not write-protected.
CONFIG6H (address:0x30000B, mask:0xE0, default:0xE0)
WRTC -- Write Protection bit (Configuration Registers) (bitmask:0x20)
WRTC = ON | 0xDF | Configuration registers are write-protected.
WRTC = OFF | 0xFF | Configuration registers are not write-protected.
WRTB -- Write Protection bit (Boot Block Memory Area) (bitmask:0x40)
WRTB = ON | 0xBF | Boot Block is write-protected.
WRTB = OFF | 0xFF | Boot Block is not write-protected.
WRTD -- Write Protection bit (Data EEPROM) (bitmask:0x80)
WRTD = ON | 0x7F | Data EEPROM is write-protected.
WRTD = OFF | 0xFF | Data EEPROM is not write-protected.
CONFIG7L (address:0x30000C, mask:0x03, default:0x03)
EBTR0 -- Table Read Protection bit Block 0 (000800-000FFF) (bitmask:0x01)
EBTR0 = ON | 0xFE | Block 0 is protected from table reads executed in other blocks.
EBTR0 = OFF | 0xFF | Block 0 is not protected from table reads executed in other blocks.
EBTR1 -- Table Read Protection bit Block 1 (001000-001FFF) (bitmask:0x02)
EBTR1 = ON | 0xFD | Block 1 is protected from table reads executed in other blocks.
EBTR1 = OFF | 0xFF | Block 1 is not protected from table reads executed in other blocks.
CONFIG7H (address:0x30000D, mask:0x40, default:0x40)
EBTRB -- Table Read Protection bit (Boot Block Memory Area) (bitmask:0x40)
EBTRB = ON | 0xBF | Boot Block is protected from table reads executed in other blocks.
EBTRB = OFF | 0xFF | Boot Block is not protected from table reads executed in other blocks.

This page generated automatically by the device-help.pl program (2022-01-30 15:56:11 UTC) from the 8bit_device.info file (rev: 1.44) of mpasmx and from the gputils source package (rev: svn Unversioned directory). The mpasmx is included in the MPLAB X.